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#### Wayne Storr

An FET constant current source is a type of active circuit which uses a

Constant current sources are commonly used in capacitor charging circuits for accurate timing purposes or in rechargeable battery charging applications, as well as linear LED circuits for driving strings of LED’s at a constant brightness. Resistive voltage references can also be formed using constant current sources, because if you know the value of the resistance and the current flowing through it is constant and steady, then you can simply use Ohm’s law to find the voltage drop. However, the key to creating an accurate and reliable

Field-effect transistors are commonly used to create a current source with Junction-FET’s (JFET’s) and Metal-oxide Semiconductor MOSFET’s already being used in low current-source applications. In its simplest form, the JFET can be used as a voltage-controlled resistor where a small gate voltage controls the conduction of its channel. We saw in our tutorial about JFET’s that JFET’s are

The image shows the standard arrangement and connections for a common source configured N-channel JFET with normal biasing when used in its active region. Here the gate-source voltage VGS is equal to the gate supply, or input voltage VG which sets the reverse bias between the gate and the source, while VDD provides the drain-to-source voltage and current flow from the supply from drain to source. This current entering the JFET drain terminal is labelled ID.

The drain-source voltage VDS is the JFET’s forward voltage drop and is a function of the drain current, ID for different gate-source values of VGS. When VDS is at its minimum value, the JFET’s conductive channel is fully open and ID is at its maximum value which is called the drain-to-source saturation current ID(sat) or simply IDSS. When VDS is at its maximum value, the JFET’s conductive channel is fully closed, (pinched-off) so ID reduces to zero with the drain-to-source voltage, VDS being equal to the drain supply voltage VDD. The gate voltage, VGS at which the JFET’s channel stops conducting is referred to as the gate cut-off voltage VGS(off).

This common source biasing arrangement of the N-channel JFET determines the steady state operation of the JFET in the absence of any input signal, VIN as VGS and ID are steady state quantities, that is the

Thus for a common-source JFET, the gate-source voltage VGS controls how much current will flow through the JFET’s conductive channel between the drain and source making the JFET a voltage-controlled device because its input voltage controls its channel current. As a result we can develop a set of output characteristic curves by plotting ID versus VGS for any given JFET device.

Then we can see that the n-channel JFET is a normally-ON device and if VGS is sufficiently negative enough, the drain-source conductive channel closes (cut-off) and the drain current reduces to zero. For the n-channel JFET, the closing of the conductive channel between drain and source is caused by the widening of the p-type depletion region around the gate until it completely closes the channel. N-type depletion regions close the channel for a p-channel JFET.

So by setting the gate-source voltage to some pre-determined fixed negative value, we can cause the JFET to conduct current through its channel at a certain value between zero amperes and IDSS respectively. Consider the circuit below.

We saw that the JFET’s output characteristics curves are a plot of ID versus VGS for a constant VDS. But we also noticed that the JFET’s curves do not change very much with large changes in VDS, and this parameter can be very useful in establishing a fixed operating point of the conductive channel.

The simplest constant current source is with the JEFT’s gate terminal shorted to its source terminal as shown, the JFET’s conductive channel is open so the flow of current through it will be close to its maximum IDSS value due to the JFET being operated in its saturated current region. However, the operation and performance of such a constant current configuration is fairly poor as the JFET is constantly in full conduction with the IDSS current value depending completely on device type.

For example, the 2N36xx or the 2N43xx n-channel JFET series is only a few mill-amperes (mA), whereas the larger n-channel J1xx or PN4xxx series can be several ten’s of milli-amperes. Also note that IDSS will vary alot between devices of the same part number as manufacturers quote on their data sheets, minimum and maximum values of this zero gate voltage drain current, IDSS.

Another point to note is that an FET is basically a voltage-controlled resistor whose conductive channel has a resistive value in series with the drain and source terminals. This channel resistance is called RDS. As we have seen, when VGS = 0, maximum drain-to-source current flows, therefore the JFET’s channel resistance, RDS must be at its minimum, and this is true.

However, the channel resistance is not completely zero but at some low ohmic value defined by the manufacturing geometry of the FET and which can be as high as 50 or so Ohms. When an FET is conducting, this channel resistance is commonly known as RDS(ON) and is at its minimum resistive value when VGS = 0. Thus a high RDS(ON) value results in a low IDSS and vice versa.

So a JFET can be biased to operate as a constant current source device at any current value below its saturation current, IDSS when VGS equals zero volts. When VGS is at its VGS(off) cut-off voltage level there will be zero drain current, (ID = 0) as the channel is closed. Thus the channels drain current, ID will always flow as long as the JFET device is operated within its active region as shown.

Note that for a P-channel JFET, the VGS(off) cut-off voltage will be a positive voltage but its saturation current, IDSS obtained when VGS equals zero volts will be the same as for an N-channel device. Also notice that the transfer curve is nonlinear because the drain current is increasing faster through the opening channel as VGS approaches zero volts.

We remember that the JFET is a depletion mode device which is always “ON”, so requires a negative gate voltage for N-channel JFET’s, and a positive gate voltage for P-channel JFET’s to turn them “OFF”. Biasing an N-channel JFET with a positive voltage, or biasing a P-channel JFET with a negative voltage will open the conductive channel even further forcing the channel current, ID beyond IDSS.

But if we use the characteristic curves of ID against VGS, we can set VGS to some negative voltage level, say -1V, -2V or -3V too create a fixed JFET constant current source of whatever current level we require between zero and IDSS. But for a more accurate constant current source with improved regulation, it is better to bias the JFET at about 10% to 50% of its maximum IDSS value. This also helps with I2*R power losses through the resistive channel and therefore reduced heating effect.

So we can see that by biasing a JFET’s gate terminal with some negative voltage value, or a positive voltage for a P-channel JFET, we can establish its operating point allowing the channel to conduct and pass a certain value of drain current, ID. For different values of VGS, a JFET drain current ID can be expressed mathematically as being:

The manufacturers datasheet for a J109 N-channel switching JFET shows that it has an IDSS of 40mA when VGS = 0, and a maximum VGS(off) value of -6.0 volts. Using these declared values, calculate the JFET’s drain current value when, VGS = 0, VGS = -2 volts, and when VGS = -5 volts. Also show the J109’s transfer characteristic curve.

1). When VGS = 0V

When VGS = 0V the conductive channel is open and maximum drain current flows.

Thus ID = IDSS =

2). When VGS = -2V

3). When VGS = -5V

4). J109 Transfer Characteristic Curve

Thus we can see that as the gate-source voltage, VGS approaches the gate-source cut-off voltage, VGS(off) the drain current, ID decreases. In this simple example, we calculated the drain current at two points, but calculating using additional values of VGS between zero and cut-off would give us a more accurate shape of the curve.

A JFET can be made to operate as a voltage controlled constant current source whenever its gate-source junction is reverse biased, and for an N-channel device we need a -VGS and for a P-channel device we need a +VGS. The problem here is that the JFET requires two separate voltage supplies, one for VDD and another for VGS. However if we place a resistor between the source and ground (0 volts), we can achieve the necessary VGS self-biasing arrangement for the JFET to operate as a constant current source using only the VDD supply voltage. Consider the circuit below.

At first glance you may think that this configuration looks very similar to a JFET common drain (source follower) circuit we saw in the . However the difference this time is that while the FET’s gate terminal is still tied directly to ground (VG = 0), the source terminal is at some voltage level above zero voltage ground due to the voltage drop across the source resistor, RS. Therefore with a channel current flowing through the external source resistor, the gate-to-source voltage of the JFET will be less than (more negative than) zero (VGS < 0).

The external source resistor, RS provides a feedback voltage which is used to self-bias the JFET’s gate terminal keeping the drain current constant through the channel despite any changes in the drain-source voltage. Thus the only voltage source we need is the supply voltage VDD to provide the drain current and bias.

So the JFET uses the voltage drop across source resistor (VRS) to set the gate bias voltage VGS and therefore the channel current as we have seen above. Thus, increasing the resistive value of RS will decrease the channels drain current ID, and vice versa. But if we wanted to construct a JFET constant current source circuit, what would be a suitable value for this external source resistor, RS.

Manufacturers data sheets for a particular N-channel JFET will give us the values of VGS(off) and IDSS. Knowing the values of these to two parameters we can transpose the above JFET equation for the drain current, ID to find the value of VGS for any given value of drain current, ID between zero and IDSS as shown.

Having found the gate-to-source voltage required for a given drain current, the value of the source biasing resitor value required is found by simply using Ohm’s law, as R = V/I. Thus:

Using the J109 N-channel JFET device from above which has an IDSS of 40mA when VGS = 0, and a maximum VGS(off) value of -6.0 volts. Calculate the value of the external source resistor required to produce a constant channel current of 20mA and again for constant current of 5mA.

1). VGS for ID = 20mA

2). VGS for ID = 5mA

Thus when VGS(off) and IDSS are both known, we can use the above equations to find the source resistance required to bias the gate voltage for a particular drain current, and in our simple example this was 87.5Ω at 20mA, and 776Ω at 5mA. So the addition of an external source resistor allows for the adjustment of the current source output.

If we was to replace the fixed value resistors with a potentiometer we can make the JFET constant current source fully adjustable. For example, we could replace the two source resistors in the above example with one 1kΩ potentiometer, or trimmer. Also as well as being fully adjustable, this JFET constant current source circuits drain current will remain constant even with changes in VDS.

An N-channel JFET is required to vary the brightness of a 5mm round red LED load between 8mA and 15mA. If the JFET constant current source circuit is fed from a 12 volt DC supply, calculate the JFET’s source resistance required to illuminated the LED between minumum and maximum brightness when the switching JFET has a maximum VGS(off) value of -4.0 volts and an IDSS of 20mA when VGS = 0. Draw the circuit diagram.

1). VGS for ID = 8mA

2). VGS for ID = 15mA

Then we would need an external potentiometer capable of varying its resistance between 67Ω and 184Ω. The nearest preferred potentiometer value would be 200Ω.

A potentiometer or trimmer used for the source resistance, RS allows us to vary or fine-tune the current flowing through JFET’s conductive channel. However, to ensure good current regulation through the FET device and therfore a stable current, it is better to limit the maximum channel current flow through the LED (15mA in this example) to between 10% and 50% of the JFETs IDSS value.

Creating constant current sources using MOSFET’s allows for much greater channel currents and better current regulation, and unlike JFET’s which are only available as normally-on depeletion mode devices, MOSFET’s are available in both depletion-mode (normally-on) and enhancement-mode (normally-off) devices as either P-channel or N-channel types allowing for a greater range of current source options.

We have seen in this tutorial about the

One of the main characteristics of a Junction Field Effect Transistor, or JFET, is that because it is a depeltion device, its conductive channel is always open so it requires a gate-to-source voltage, VGS to turn it “OFF”. The VGS(off) voltage required for an N-channel JFET ranges from 0 volts for full conduction of the channel to some negative value, usually several volts, to turn the JFET fully-OFF, closing the channel. Thus biasing the gate terminal at some fixed value inbetween zero and VGS(off), we can control the channels depletion layers width and therefore its resistive value, passing a fixed and constant amount of current. For a P-channel JFET, its VGS(off) value ranges from 0 volt for full channel conduction to some positive value of several volts for a particular VDS value.

The regulation and tolerance of the constant current for a given JFET device is related to the amount of drain current, ID passing through the channel. The lower the drain current through a particular devive, the better the regulation. Biasing a JFET at between about 10% to 50% of its maximum IDSS value will improve the devices regulation and performance. This is achieved by connected an external resististance between the source and gate terminals.

A gate-to-source feedback resistor as shown above, provides the necessary self-biasing of the JFET allowing it to operate as a constant current source at any current level well below its saturation current, IDSS. This external source resistance, RS can of a fixed resistive value or variable using a potentiometer.

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*Field Effect Transistor*to supply a constant amount of current to a circuit. But why would you want a constant current?*Constant current sources*and current sinks, (a current sink is the reverse of a current source) are a very simple way of forming biasing circuits or voltage references with a constant value of current, for example, 100uA, 1mA or 20mA using just a single FET and resistor.Constant current sources are commonly used in capacitor charging circuits for accurate timing purposes or in rechargeable battery charging applications, as well as linear LED circuits for driving strings of LED’s at a constant brightness. Resistive voltage references can also be formed using constant current sources, because if you know the value of the resistance and the current flowing through it is constant and steady, then you can simply use Ohm’s law to find the voltage drop. However, the key to creating an accurate and reliable

*constant current source*depends on using low transconductance FET’s as well as precision resistor values to convert the current into a precise and stable voltage.Field-effect transistors are commonly used to create a current source with Junction-FET’s (JFET’s) and Metal-oxide Semiconductor MOSFET’s already being used in low current-source applications. In its simplest form, the JFET can be used as a voltage-controlled resistor where a small gate voltage controls the conduction of its channel. We saw in our tutorial about JFET’s that JFET’s are

*depletion devices*and that the N-channel JFET is a “normally-ON” device, until the gate-to-source voltage (VGS) becomes negative enough to turn it “OFF”. The P-channel JFET which is also a “normally-ON” depletion device requires the gate voltage to become positive enough to turn it “OFF”.**N-channel JFET Biasing**
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The image shows the standard arrangement and connections for a common source configured N-channel JFET with normal biasing when used in its active region. Here the gate-source voltage VGS is equal to the gate supply, or input voltage VG which sets the reverse bias between the gate and the source, while VDD provides the drain-to-source voltage and current flow from the supply from drain to source. This current entering the JFET drain terminal is labelled ID.

The drain-source voltage VDS is the JFET’s forward voltage drop and is a function of the drain current, ID for different gate-source values of VGS. When VDS is at its minimum value, the JFET’s conductive channel is fully open and ID is at its maximum value which is called the drain-to-source saturation current ID(sat) or simply IDSS. When VDS is at its maximum value, the JFET’s conductive channel is fully closed, (pinched-off) so ID reduces to zero with the drain-to-source voltage, VDS being equal to the drain supply voltage VDD. The gate voltage, VGS at which the JFET’s channel stops conducting is referred to as the gate cut-off voltage VGS(off).

This common source biasing arrangement of the N-channel JFET determines the steady state operation of the JFET in the absence of any input signal, VIN as VGS and ID are steady state quantities, that is the

*quiescent state*of the JFET.Thus for a common-source JFET, the gate-source voltage VGS controls how much current will flow through the JFET’s conductive channel between the drain and source making the JFET a voltage-controlled device because its input voltage controls its channel current. As a result we can develop a set of output characteristic curves by plotting ID versus VGS for any given JFET device.

**N-channel JFET Output Characteristic**
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**The JFET as a Constant Current Source**Then we can see that the n-channel JFET is a normally-ON device and if VGS is sufficiently negative enough, the drain-source conductive channel closes (cut-off) and the drain current reduces to zero. For the n-channel JFET, the closing of the conductive channel between drain and source is caused by the widening of the p-type depletion region around the gate until it completely closes the channel. N-type depletion regions close the channel for a p-channel JFET.

So by setting the gate-source voltage to some pre-determined fixed negative value, we can cause the JFET to conduct current through its channel at a certain value between zero amperes and IDSS respectively. Consider the circuit below.

**JFET Zero-voltage Biasing**
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We saw that the JFET’s output characteristics curves are a plot of ID versus VGS for a constant VDS. But we also noticed that the JFET’s curves do not change very much with large changes in VDS, and this parameter can be very useful in establishing a fixed operating point of the conductive channel.

The simplest constant current source is with the JEFT’s gate terminal shorted to its source terminal as shown, the JFET’s conductive channel is open so the flow of current through it will be close to its maximum IDSS value due to the JFET being operated in its saturated current region. However, the operation and performance of such a constant current configuration is fairly poor as the JFET is constantly in full conduction with the IDSS current value depending completely on device type.

For example, the 2N36xx or the 2N43xx n-channel JFET series is only a few mill-amperes (mA), whereas the larger n-channel J1xx or PN4xxx series can be several ten’s of milli-amperes. Also note that IDSS will vary alot between devices of the same part number as manufacturers quote on their data sheets, minimum and maximum values of this zero gate voltage drain current, IDSS.

Another point to note is that an FET is basically a voltage-controlled resistor whose conductive channel has a resistive value in series with the drain and source terminals. This channel resistance is called RDS. As we have seen, when VGS = 0, maximum drain-to-source current flows, therefore the JFET’s channel resistance, RDS must be at its minimum, and this is true.

However, the channel resistance is not completely zero but at some low ohmic value defined by the manufacturing geometry of the FET and which can be as high as 50 or so Ohms. When an FET is conducting, this channel resistance is commonly known as RDS(ON) and is at its minimum resistive value when VGS = 0. Thus a high RDS(ON) value results in a low IDSS and vice versa.

So a JFET can be biased to operate as a constant current source device at any current value below its saturation current, IDSS when VGS equals zero volts. When VGS is at its VGS(off) cut-off voltage level there will be zero drain current, (ID = 0) as the channel is closed. Thus the channels drain current, ID will always flow as long as the JFET device is operated within its active region as shown.

**JFET Transfer Curve**
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Note that for a P-channel JFET, the VGS(off) cut-off voltage will be a positive voltage but its saturation current, IDSS obtained when VGS equals zero volts will be the same as for an N-channel device. Also notice that the transfer curve is nonlinear because the drain current is increasing faster through the opening channel as VGS approaches zero volts.

**JFET Negative-voltage Biasing**
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We remember that the JFET is a depletion mode device which is always “ON”, so requires a negative gate voltage for N-channel JFET’s, and a positive gate voltage for P-channel JFET’s to turn them “OFF”. Biasing an N-channel JFET with a positive voltage, or biasing a P-channel JFET with a negative voltage will open the conductive channel even further forcing the channel current, ID beyond IDSS.

But if we use the characteristic curves of ID against VGS, we can set VGS to some negative voltage level, say -1V, -2V or -3V too create a fixed JFET constant current source of whatever current level we require between zero and IDSS. But for a more accurate constant current source with improved regulation, it is better to bias the JFET at about 10% to 50% of its maximum IDSS value. This also helps with I2*R power losses through the resistive channel and therefore reduced heating effect.

So we can see that by biasing a JFET’s gate terminal with some negative voltage value, or a positive voltage for a P-channel JFET, we can establish its operating point allowing the channel to conduct and pass a certain value of drain current, ID. For different values of VGS, a JFET drain current ID can be expressed mathematically as being:

**JFET Drain Current Equation**
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**FET Constant Current Source Example No1**The manufacturers datasheet for a J109 N-channel switching JFET shows that it has an IDSS of 40mA when VGS = 0, and a maximum VGS(off) value of -6.0 volts. Using these declared values, calculate the JFET’s drain current value when, VGS = 0, VGS = -2 volts, and when VGS = -5 volts. Also show the J109’s transfer characteristic curve.

1). When VGS = 0V

When VGS = 0V the conductive channel is open and maximum drain current flows.

Thus ID = IDSS =

**40mA**.2). When VGS = -2V

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3). When VGS = -5V

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4). J109 Transfer Characteristic Curve

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Thus we can see that as the gate-source voltage, VGS approaches the gate-source cut-off voltage, VGS(off) the drain current, ID decreases. In this simple example, we calculated the drain current at two points, but calculating using additional values of VGS between zero and cut-off would give us a more accurate shape of the curve.

**JFET Current Source**A JFET can be made to operate as a voltage controlled constant current source whenever its gate-source junction is reverse biased, and for an N-channel device we need a -VGS and for a P-channel device we need a +VGS. The problem here is that the JFET requires two separate voltage supplies, one for VDD and another for VGS. However if we place a resistor between the source and ground (0 volts), we can achieve the necessary VGS self-biasing arrangement for the JFET to operate as a constant current source using only the VDD supply voltage. Consider the circuit below.

**JFET Current Source**
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At first glance you may think that this configuration looks very similar to a JFET common drain (source follower) circuit we saw in the . However the difference this time is that while the FET’s gate terminal is still tied directly to ground (VG = 0), the source terminal is at some voltage level above zero voltage ground due to the voltage drop across the source resistor, RS. Therefore with a channel current flowing through the external source resistor, the gate-to-source voltage of the JFET will be less than (more negative than) zero (VGS < 0).

The external source resistor, RS provides a feedback voltage which is used to self-bias the JFET’s gate terminal keeping the drain current constant through the channel despite any changes in the drain-source voltage. Thus the only voltage source we need is the supply voltage VDD to provide the drain current and bias.

So the JFET uses the voltage drop across source resistor (VRS) to set the gate bias voltage VGS and therefore the channel current as we have seen above. Thus, increasing the resistive value of RS will decrease the channels drain current ID, and vice versa. But if we wanted to construct a JFET constant current source circuit, what would be a suitable value for this external source resistor, RS.

Manufacturers data sheets for a particular N-channel JFET will give us the values of VGS(off) and IDSS. Knowing the values of these to two parameters we can transpose the above JFET equation for the drain current, ID to find the value of VGS for any given value of drain current, ID between zero and IDSS as shown.

**JFET Gate to Source Voltage Equation**
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Having found the gate-to-source voltage required for a given drain current, the value of the source biasing resitor value required is found by simply using Ohm’s law, as R = V/I. Thus:

**JFET Source Resistor Equation**
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**FET Constant Current Source Example No2**Using the J109 N-channel JFET device from above which has an IDSS of 40mA when VGS = 0, and a maximum VGS(off) value of -6.0 volts. Calculate the value of the external source resistor required to produce a constant channel current of 20mA and again for constant current of 5mA.

1). VGS for ID = 20mA

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2). VGS for ID = 5mA

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Thus when VGS(off) and IDSS are both known, we can use the above equations to find the source resistance required to bias the gate voltage for a particular drain current, and in our simple example this was 87.5Ω at 20mA, and 776Ω at 5mA. So the addition of an external source resistor allows for the adjustment of the current source output.

If we was to replace the fixed value resistors with a potentiometer we can make the JFET constant current source fully adjustable. For example, we could replace the two source resistors in the above example with one 1kΩ potentiometer, or trimmer. Also as well as being fully adjustable, this JFET constant current source circuits drain current will remain constant even with changes in VDS.

**FET Constant Current Source Example No3**An N-channel JFET is required to vary the brightness of a 5mm round red LED load between 8mA and 15mA. If the JFET constant current source circuit is fed from a 12 volt DC supply, calculate the JFET’s source resistance required to illuminated the LED between minumum and maximum brightness when the switching JFET has a maximum VGS(off) value of -4.0 volts and an IDSS of 20mA when VGS = 0. Draw the circuit diagram.

1). VGS for ID = 8mA

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2). VGS for ID = 15mA

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Then we would need an external potentiometer capable of varying its resistance between 67Ω and 184Ω. The nearest preferred potentiometer value would be 200Ω.

**Adjustable JFET Constant Current Source**
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A potentiometer or trimmer used for the source resistance, RS allows us to vary or fine-tune the current flowing through JFET’s conductive channel. However, to ensure good current regulation through the FET device and therfore a stable current, it is better to limit the maximum channel current flow through the LED (15mA in this example) to between 10% and 50% of the JFETs IDSS value.

Creating constant current sources using MOSFET’s allows for much greater channel currents and better current regulation, and unlike JFET’s which are only available as normally-on depeletion mode devices, MOSFET’s are available in both depletion-mode (normally-on) and enhancement-mode (normally-off) devices as either P-channel or N-channel types allowing for a greater range of current source options.

**FET Constant Current Source Summary**We have seen in this tutorial about the

**FET Constant Current Source**that due to their channel resistance characteristics, field effect transistors can be used to supply a constant current to a load and find numerous applications in electronics circuits where it is required to supply a fixed current to a connected load. Constant current circuits can be built using depletion mode FET’s but also using BJT’s (*bipolar junction transistors)*, or a combination of these two devices. Remembering that the JFET is a voltage-controlled device, not a current-controlled device like the bipolar junction transistor.One of the main characteristics of a Junction Field Effect Transistor, or JFET, is that because it is a depeltion device, its conductive channel is always open so it requires a gate-to-source voltage, VGS to turn it “OFF”. The VGS(off) voltage required for an N-channel JFET ranges from 0 volts for full conduction of the channel to some negative value, usually several volts, to turn the JFET fully-OFF, closing the channel. Thus biasing the gate terminal at some fixed value inbetween zero and VGS(off), we can control the channels depletion layers width and therefore its resistive value, passing a fixed and constant amount of current. For a P-channel JFET, its VGS(off) value ranges from 0 volt for full channel conduction to some positive value of several volts for a particular VDS value.

The regulation and tolerance of the constant current for a given JFET device is related to the amount of drain current, ID passing through the channel. The lower the drain current through a particular devive, the better the regulation. Biasing a JFET at between about 10% to 50% of its maximum IDSS value will improve the devices regulation and performance. This is achieved by connected an external resististance between the source and gate terminals.

A gate-to-source feedback resistor as shown above, provides the necessary self-biasing of the JFET allowing it to operate as a constant current source at any current level well below its saturation current, IDSS. This external source resistance, RS can of a fixed resistive value or variable using a potentiometer.

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**نام موضوع**: FET Current Source

**دسته**: electronic